1. Field of the Invention
The present invention relates to a constant potential generating circuit and a semiconductor device using the same constant potential generating circuit, and more specifically to a constant potential generating circuit which can increase drive capability and is suitable for control stability, in particular when an intermediate potential is generated, and a semiconductor device using the same constant potential generating circuit.
2. Description of the Prior Art
FIG. 22 is a circuit diagram showing a prior art constant potential generating circuit device which can increase the capability of outputting any required intermediate potential. In the drawing, a series circuit of a P-channel transistor P11 and an N-channel transistor N11 is connected between a supply potential V.sub.DD and a ground potential V.sub.SS, and any determined intermediate output potential V.sub.out can be outputted from a junction point between the two drains of the transistor P11 and the transistor N11. The output potential V.sub.out is supplied to a load which requires an intermediate potential. On the other hand, a predetermined intermediate reference potential V.sub.ref and the output potential V.sub.out of this circuit are both given to a differential amplifier circuit Ad, and two control voltages are outputted from the differential amplifier circuit Ad to a node 11 and another node 12, respectively. Further, the control voltage at the node 11 is given to the gate of the transistor P11, and the control voltage at the node 12 is given to the gate of the transistor N11.
The operation of the circuit constructed as described above will be described hereinbelow with reference to some waveform diagrams shown in FIGS. 23(a) to 23(c), in which FIG. 23(a) shows the operation obtained when the output potential V.sub.out is higher than the reference potential V.sub.ref ; FIG. 23(b) shows the operation obtained when the output potential V.sub.out is lower than the reference potential V.sub.ref ; and FIG. 23(c) shows the operation obtained when the output potential V.sub.out is oscillated on the basis of the reference potential V.sub.ref.
Now, when the output potential V.sub.out is roughly the same in level as the reference potential V.sub.ref ; that is, when the circuit is at a stable point, the potential at the node 11 is at roughly the supply potential V.sub.DD and the potential at the node 12 is at roughly the ground potential V.sub.SS, so that both the transistors P11 and N11 are turned off.
Here, the differential amplifier circuit Ad compares the output potential V.sub.out with the reference potential V.sub.ref, and controls the gate voltages of the transistor P11 and the transistor N11 in such a way that the output potential V.sub.out becomes equal to the reference potential V.sub.ref.
Now, when the output potential V.sub.out is higher than the reference potential V.sub.ref. as shown in FIG. 23(a), the differential amplifier circuit Ad detects the difference between the two and operates so that the node 12 can be pulled up from a low level. As a result, the transistor N11 is turned on to pull down the level of the output potential V.sub.out.
Consequently, when the output potential level V.sub.out reaches the reference potential level V.sub.ref, the differential amplifier circuit Ad pulls down the node 12 to a low level, with the result that the output potential V.sub.out approaches the reference potential V.sub.ref, and thereby a stable point can be obtained.
Further, when being lowered, if the output potential V.sub.out is dropped excessively below the reference potential V.sub.ref, the differential amplifier circuit Ad operates for correction by pulling down the node 11 from the supply potential V.sub.DD, so that the output potential V.sub.out can be returned up to the reference potential V.sub.ref.
In contrast with this, when the output potential V.sub.out is lower than the reference potential V.sub.ref as shown in FIG. 23(b), the differential amplifier circuit Ad detects the difference between the two and operates so that the node 11 can be pulled down from a high level. As a result, the transistor P11 is turned on to pull up the level of the output potential V.sub.out.
Consequently, when the output potential level V.sub.out reaches the reference potential level V.sub.ref, the differential amplifier circuit Ad pulls up the node 11 to a high level, with the result that the output potential V.sub.out approaches the reference potential V.sub.ref, and thereby a stable point can be obtained.
Further, when being raised, if the output potential V.sub.out rises excessively beyond the reference potential V.sub.ref, the differential amplifier circuit Ad operates for correction by pulling up the node 12 from the ground potential V.sub.SS, so that the output potential V.sub.out can be returned down to the reference potential V.sub.ref.
In the prior art semiconductor device as described above, however, there exists a problem as follows: In the circuit construction as shown in FIG. 22, when the capability of both the transistors P11 and N11 for deciding the output potential V.sub.out is increased, the level change speed of the output potential V.sub.out increases. When the level change speed increases, there exists a possibility such that since the differential amplifier circuit Ad detects the difference between the reference potential V.sub.ref and the output potential V.sub.out, the level change speed at the output potential V.sub.out increases higher than the level control speed at the node 11 or 12. The situation as described above occurs more prominently with increasing driving capability of the transistors P11 and N11 (in order to increase the driving capability of the output potential V.sub.out outputted as an intermediate level). As a result, before converging to the reference potential V.sub.ref, the output potential V.sub.out overshoots or undershoots, with the result that the stabilization of the output potential V.sub.out at the reference potential V.sub.ref is delayed. When this situation becomes extremely, the output potential V.sub.out overshoots and undershoots repeatedly, as shown in FIG. 23(c), and thereby the control voltages at the nodes 11 and 12 both oscillate, with the result that it is impossible to stabilize the level of the output potential V.sub.out.
To overcome this problem, it is necessary to reduce the change speed of the output potential V.sub.out sufficiently slower than the level detection speed of the differential amplifier circuit Ad. For this purpose, it is necessary to lower the driving capability of the transistors P11 and N11 or to change the response speed to the level change of the output potential V.sub.out with respect to time, according to the level difference between the output potential V.sub.out and the reference potential V.sub.ref. However, when the driving capability of the output transistors is lowered, the original object of increasing the driving capability of the intermediate potential cannot be achieved. On the other hand, when the circuit response characteristics are changed according to the level change or with the elapse of time, it is difficult to set the circuit constants, so that the circuit may be operated erroneously, thus resulting in various undesired problems.